Adder Nfet Average Nloc Time (s) Average Width 3.3. Overview of Near-optimal Stis Algorithm 4.1. Transistor Sizing 4.2. Comparison between Stis and Other Sizing Schemes

Critical Delay (ns) min width opt width 2bit 66 6.82 Table 1. Critical delay comparison between the minimum-width solution and the optimal-width solution. Table 2. Critical delay comparison among minimal sizing scheme, transistor sizing only, and the STIS solution. the maximum number of the possible evaluations for any xi(i = f1; ; ng), the LRA scheme will converge in the polynomial time O(r n 3). 3.2. Implementation of the DP-slope model We assume a DP-slope model of the most general form with the only requirement to give the unit eeective resistance r0 for each discrete transistor size and apply a table based method in order to achieve the satisfactory trade-oo between accuracy and complexity. In general, the eeective unit resistance r0 of a transistor is a function of its size, the input waveform slope and the capacitance loading. However , 17] proposed that all the three parameters could be combined into one factor called slope ratio to solely determine the unit eeective resistance r0 for the transistor. Thus, a one-dimensional table can be used instead of a three-dimensional table. We built a one-dimensional table for every type of transistors based on SPICE simulation results. Our implementation is similar to that in 16]. The overall STIS algorithm includes three steps: to initialize the coeecient functions, to tighten lower and upper bounds of the optimal solution and to search the optimal solution between the LR-tight lower and upper bounds. Besides , the coeecient functions will be updated during the procedure to tighten lower and upper bounds because the unit eeective r0 for the transistor under the DP-slope model is a function of the current solution X. In order to eeciently initialize and update the coeecient functions, a circuit containing both transistors and interconnects is pre-partitioned into DCCs. Although the sizes of coeecient function F0 and F1 are n n, their operation complexities are reduced greatly by DCC partitioning because these coeecients are only needed to be computed for transistors and wires within a DCC. It is worthwhile to mention that the LR-tight lower and upper bounds have the zero sensitivity. In other words, the sensitivity based method can not obtain a solution more optimized than the LR-tight lower or upper bound. If the LR-tight lower and upper bounds are identical for every transistor/wire, the optimal solution is achieved immediately , which happens almost all cases in practice. Because both the coeecient operations …